Many memory manufacturers are trying to develop nonvolatile memory circuits that are both small enough and fast enough to replace traditional nonvolatile storage media such as magnetic hard drives. Such nonvolatile memory circuits include flash erasable and programmable read-only memory (flash-EPROM) and flash electrically erasable and programmable read-only memory (flash-EEPROM).
Unfortunately, many flash memories have relatively slow write speeds and relatively small storage capacities because they must precisely erase their memory cells to avoid offset currents, which, if high enough, can corrupt data during a read cycle. Because the erase routine is relatively long and must be done before each program cycle, it increases the write time, and thus reduces the write speed, of a flash memory.
FIG. 1 is a schematic diagram of a read circuit that increases the write speed of a flash memory by eliminating the need for the lengthy erase procedure. Specifically, a read circuit 10 compensates for offset currents generated in a bit line 12 by memory cells 14, only one of which is shown in FIG. 1 for clarity. If an offset current is flowing in the bit line 12, it will cause an offset-voltage drop across a load transistor 16. Therefore, before a memory cell 14 is activated for reading, i.e., before a word line WL coupled to the cell 14 is driven active high, a control signal activates a transistor 18 so that an offset current flowing in the bit line 12 will cause a current to flow through the transistor 18 and charge a capacitor 20 to the offset voltage generated across the load 16. After the capacitor 20 charges to the offset voltage, the transistor 18 is deactivated. Because the input terminals of a comparator 22 are high impedance, the capacitor 20 holds its charge. Next, WL is driven high to activate both the memory cell 14, which generates a read current through the load 16, and a reference cell 24, which generates a reference current through a load 26. Thus, the read current generates a read voltage at a node 27, and the reference current generates a reference voltage at a node 28. The voltage drop at the node 27 caused by the offset current through the load 16, however, is canceled by the offset voltage stored on the capacitor 20. Therefore, the comparator 22 compares the true read voltage (the read voltage without any offset component) with the reference voltage to generate a data signal. Thus, by compensating for offset currents generated by the memory cells 14, the circuit 10 prevents read errors without requiring that all of the cells 14 be precisely erased to eliminate such offset currents.
Still referring to FIG. 1, a transistor 29 and capacitor 30 can compensate for an offset current drawn by the reference cell 24. But even if the cell 24 does not draw an offset current, the transistor 28 and capacitor 30 can be included to balance the impedances at the input terminals of the comparator 22. A circuit similar to the read circuit 10 is discussed in U.S. Pat. No. 5,729,492 to Campardo, which is incorporated by reference.
A problem with the circuit 10, however, is that the capacitors 20 and 30 may be relatively bulky and thus occupy a relatively large die area, or may increase the complexity of the manufacturing process. Furthermore, the reference cell or cells 24 also occupy a significant die area and often must be calibrated by performing a lengthy and complex procedure during testing of the circuit 10.